View NJ88C21_1081420.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NJ8821
DS3278-1.3
NJ8821
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE) WITH RESETTABLE COUNTERS
The NJ8821 is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable `M' counter, 7-bit programmable `A' counter and the necessary control and latch circuitry for accepting and latching the input data. Data is presented as eight 4-bit words under external control from a suitable microprocessor.. It is intended to be used in conjunction with a two-modulus prescaler such as the SP8710 series to produce a universal binary coded synthesiser. The NJ8821 is available in Plastic DIL (DP) and Miniature Plastic DIL (MP) packages, both with operating temperature range of 230C to 170C. The NJ8821MA is available only in Ceramic DIL package with operating temperature range of 240C to 185C.
PDA PDB LD FIN VSS VDD OSC IN OSC OUT D0 D1 1 2 3 4 5 20 19 18 17 16 CH RB MC DS2 DS1 DS0 PE NC D3 D2
NJ8821
6 7 8 9 10 15 14 13 12 11
DP20, MP20 DG20
FEATURES
Fig.1 Pin connections - top view
s s s s
Low Power Consumption Microprocessor Compatible High Performance Sample and Hold Phase Detector >10MHz Input Frequency ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD2VSS Input voltage Open drain output, pin 3 All other pins Storage temperature Storage temperature 20*5V to 7V 7V VSS20*3V to VDD10*3V 265C to 1150C (DG package, NJ8821MA) 255C to 1125C (DP and MP packages, NJ8821)
ORDERING INFORMATION
NJ8821 BA DP Plastic DIL Package NJ8821 BA MP Miniature Plastic DIL Package NJ8821 MA DG Ceramic DIL Package
DATA SELECT INPUTS DS0 DS1 DS2 15 PROGRAM ENABLE (PE) 14 LATCH SELECT LOGIC 16 17 TO INTERNAL LATCHES fr
RB 19
CH 20
OSC IN OSC OUT
7 8
REFERENCE COUNTER (11BITS)
42
SAMPLE/HOLD PHASE DETECTOR FREQUENCY/ PHASE DETECTOR
1
PDA
LATCH 6 LATCH 7 LATCH 8
2
D0 DATA D1 INPUTS D2 D3
9 10 11 12
PDB
3 VSS
LOCK DETECT (LD)
LATCH 4 LATCH 5
LATCH 1 LATCH 2 LATCH 3
FIN
4
`A' COUNTER (7 BITS)
`M' COUNTER (10 BITS)
fv
VDD VSS
6
CONTROL LOGIC 5
18
MODULUS CONTROL OUTPUT (MC)
Fig.2 Block diagram
NJ8821
ELECTRICAL CHARACTERISTICS AT VDD = 5V
Test conditions unless otherwise stated: VDD-VSS=5V 0*5V. Temperature range NJ8821 BA: -30C to +70C; NJ8821MA: -40C to +85C DC Characteristics Characteristic Min. Supply current OUTPUT LEVELS Modulus Control Output (MC) High level Low level Lock Detect Output (LD) Low level Open drain pull-up voltage PDB Output High level Low level 3-state leakage current INPUT LEVELS Data Inputs (D0-D3) High level Low level Program Enable Input (PE) High level Low level Data Select Inputs (DS0-DS2) High level Low level AC Characteristics Characteristic Min. FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propagation delay, clock to MC Strobe pulse width, tW(ST) Data set-up time, tDS Data hold time, tDH Latch address set-up time, tSE Latch address hold time, tHE Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Output resistance, PDA Digital phase detector gain 200 10*6 30 2 1 1 1 1 500 5 1 5 0*4 50 Value Typ. Max. Units Conditions Value Typ. 3*5 0*7 Max. 5*5 1*5 mA mA Units Conditions fosc, fFIN = 10MHz fosc, fFIN = 1*0MHz 0 to 5V square wave
4*6 0*4 0*4 7 4*6 0*4 0*1
V V V V V V A
ISOURCE = 1mA ISINK = 1mA ISINK = 4mA
ISOURCE = 5mA ISINK = 5mA
4*25 0*4 4*25 0*75 4*25 0*75
V V V V V V
TTL compatible See note 1
mVRMS 10MHz AC-coupled sinewave MHz Input squarewave VDD to VSS, See note 4. ns See note 2. s s See Fig. 6 s s s ns See note 3. k nF k V/Rad
NOTES 1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and `on' resistance of the sample switch driving this pin will add a finite time constant to the loop. An external 1nF hold capacitor will give a maximum time constant of 5s, typically. 4. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed.
2

NJ8821
PIN DESCRIPTIONS
Pin no. 1 Name PDA Description Analog output from the sample and hold phase comparator for use as a `fine' error signal. Output at (VDD2VSS)/2 when the system is in lock. Voltage increases as fv phase lead increases; voltage decreases as fr phase lead increases. Output is linear over only a narrow phase window, determined by gain (programmed by RB). Three-state output from the phase/frequency detector for use as a `coarse' error signal. fv. fr or fv leading: positive pulses with respect to the bias point VBIAS fv , fr or fr leading: negative pulses with respect to the bias point VBIAS fv = fr and phase error within PDA window: high impedance. An open-drain lock detect output at low level when phase error is within PDA window (in lock); high impedance at all other times. The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when a full logic swing is available, may be DC-coupled. Negative supply (ground). Positive supply.
2
PDB
3 4 5 6 7, 8
LD FIN VSS VDD
OSC IN/ These pins form an on-chip reference oscillator when a series resonant crystal is connected across OSC OUT them. Capacitors of appropriate value are also required between each end of the crystal and ground to provide the necessary additional phase shift. An external reference signal may, alternatively, be applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being twice the programmed number. D0-D3 NC PE DS0-DS2 MC Data on these inputs is transferred to the internal data latches during the appropriate data read time slot. D3 is MSB, D0 is LSB. No connection This pin is used as a strobe for the data. A logic `1' on this pin transfers data from the D0-D3 pins to the internal latch addressed by the data select (DS0-DS2) pins . A logic `0' disables the data inputs. Data select inputs for addressing the internal data latches Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning of a count cycle and will remain low until the `A' counter completes its cycle. MC then goes high and remains high until the `M' counter completes its cycle, at which point both `A' and `M' counters are reset. This gives a total division ratio of MP1A, where P and P11 represent the dual-modulus prescaler values. The program range of the `A' counter is 0-127 and therefore can control prescalers with a division ratio up to and including 4128/129. The programming range of the `M' counter is 8-1023 and, for correct operation, M>A. Where every possible channel is required, the minimum total division ratio should be P 22P. An external sample and hold phase comparator gain programming resistor should be connected between this pin and VSS. An external hold capacitor should be connected between this pin and VSS.
8 VDD = 5V OSC IN, FIN = 0V TO 5V SQUARE WAVE 7 SUPPLY CURRENT (mA) 6 5 10MHz 4 1MHz 3 2 TOTAL SUPPLY CURRENT IS THE SUM OF THAT DUE TO FIN AND OSC IN 1 2 3 4 5 6 7 INPUT FREQUENCY (MHz) 8 9 10 1 VDD = 5V FIN = LOW FREQUENCY 0V TO 5V SQUARE WAVE
9,10, 11, 12 13 14 15, 16, 17 18
19 20
2*0
RB CH
SUPPLY CURRENT (mA)
1*5
OSC IN 1*0 FIN 0*5
0*2
0*4
0*6 0*8 1*0 1*2 INPUT LEVEL (V RMS)
1*4
1*6
Fig. 3 Typical supply current v. input frequency
Fig. 4 Typical supply current v. input level, OSC IN
3
NJ8821
PROGRAMMING
Timing is generated externally, normally from a microprocessor, and allows the user to change the data in selected latches as defined by the data map Fig.5. The PE pin is used as a strobe for the data: taking PE high causes data to be transferred from the data pins (D0-D3) into the addressed latch. Following the falling edge of PE, the data is retained in the addressed latch and the data inputs are disabled. Data transfer from all internal latches into the counters occurs simultaneously with the transfer of data into latch 1, which would therefore normally be the last latch addressed during each channel change. Timing information for this mode of operation is given in Fig. 6. When re-programming, a reset to zero state is followed by reloading with the new counter values. This means that the synthesiser loop lock-up time is well defined and less than 10ms. If shorter lock-up times are are required when making only small changes in frequency, the GPS NJ8823 (with nonresettable counters) should be considered. WORD DS2 1 2 3 4 5 6 7 8 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 1 DS0 0 1 0 1 0 1 0 1 D3 M1 M5 M9 A3 R3 R7 D2 M0 M4 M8 A2 A6 R2 R6 R10 D1 M3 M7 A1 A5 R1 R5 R9 D0 M2 M6 A0 A4 R0 R4 R8
Fig. 5 Data map
DS0-DS2
PE
D0 - D3
tDS tSE tW(ST)
tDH tHE
Fig. 6 Timing diagram
PHASE COMPARATORS
The digital phase/frequency detector drives a three-state output, PDB, which provides a `coarse' error signal to enable fast switching between channels. The PDB output is active until the phase error is within the sample and hold phase detector, PDA, window, when PDB becomes high impedance. Phase-lock is indicated at this point by a low level on LD. The sample and hold phase detector provides a `fine' error signal to give further phase adjustment and to hold the loop in lock. An internally generated ramp, controlled by the digital output from both the reference and main divider chains, is sampled at the reference frequency to give the `fine' error signal, PDA. When in phase lock, this output would be typically at (VDD2VSS)/2 and any offset from this would be proportional to phase error. The relationship between this offset and the phase error is the phase comparator gain, which is programmable with an external resistor, RB. An internal 50pF capacitor is used in the sample and hold comparator.
CRYSTAL OSCILLATOR
When using the internal oscillator, the stability may be enhanced at high frequencies by the inclusion of a resistor between pin 8 (OSC OUT) and the other components. A value of 150-270 is advised.
PROGRAMMING/POWER UP
Data and signal input pins should not have input applied to them prior to the application of VDD, as otherwise latch-up may occur.
4
NJ8821
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES * FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 * NORTH AMERICA Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. * SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 * SWEDEN Stockholm, Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * TAIWAN, ROC Taipei Tel: 886 2 5461260. Fax: 886 2 71900260 * UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1992
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of NJ88C21

	To Download NJ88C21 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .